`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    14:35:28 09/03/2012 
// Design Name: 
// Module Name:    Divider 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module Divider (
 clock ,rst,
 clock1hz 
  );
  //24999999
 input clock,rst;
 output clock1hz;
 reg clock1hz;
 reg [25:0] counter_out ;
 
 initial begin
	counter_out=0;
	clock1hz=0;
 end
 
   always @(posedge clock)
		if(counter_out==24999999)
			begin
				clock1hz<=~clock1hz;
				counter_out <= 0;
			end
      else if(rst)
			begin	
				clock1hz <= 0; 
				counter_out <= 0;
			end
      else
        counter_out <= counter_out + 1;

 
						
 endmodule 
